Block puncturing for turbo code based incremental redundancy

ABSTRACT

A method of block puncturing for turbo code based incremental redundancy includes a first step ( 1200 ) of coding an input data stream into systematic bits and parity bits. A next step ( 1202 ) includes loading the systematic bits and parity bits into respective systematic and parity block interleavers in a column-wise manner. A next step ( 1204 ) includes selecting a predefined redundancy. A next step ( 1206 ) includes outputting bits from the block interleavers in a row-wise manner in accordance with the selected predefined redundancy.

FIELD OF THE INVENTION

This invention relates generally to communication systems, and more particularly to coding in a turbo coded communication system.

BACKGROUND OF THE INVENTION

Convolutional codes are often used in digital communication systems to protect transmitted information from error. Such communication systems include the Direct Sequence Code Division Multiple Access (DS-CDMA) standard IS-95, the Global System for Mobile Communications (GSM), and next generation wideband communication systems. Typically in these systems, a signal is convolutionally coded into an outgoing code vector that is transmitted. At a receiver, a decoder, such as a Viterbi decoder as is known in the art, uses a trellis structure to perform an optimum search for the transmitted signal bits based on maximum likelihood criterion.

More recently, turbo codes have been developed that outperform conventional coding techniques. Turbo codes are generally composed of two or more convolutional codes and turbo interleavers. Correspondingly, turbo decoding is iterative and uses a soft output decoder to decode the individual convolutional codes. The soft outputs of the decoders are used in the decoding procedure to iteratively approach the converged final results.

FIG. 1 shows a typical turbo encoder that is constructed with one interleaver and two constituent codes which are recursive systematic convolutional (RSC) codes, but can be block codes, also. A turbo encoder is shown which is a parallel concatenation of two RSCs with an interleaver, π, between them. The output, c_(k), of the turbo encoder is generated by multiplexing (concatenating) the information bits, b_(k), and parity bits, P_(1k) and p_(2k), from the two encoders. Typically, the parity bits are punctured as is known in the art to increase code rate. Each RSC has a one parity bit output, but the number of parity bits of the RSC can be more than one.

Typically, the encoded data is transmitted to a receiver, which uses error detection. If an error is detected, the receiver can request that the transmitter, such as a base station for example, retransmit the data using an Automatic Repeat Request (ARQ). In other words, if a receiver is not able to resolve (converge on) the data bits in time, the radio can request the transmitter to resend that portion of bits from the block or a portion of a frame of data that failed so as to be properly decoded. There are several known techniques to provide ARQ. In addition, there can be ARQ combining of different transmissions. Further, the receiver can attempt to provide error correction as well as error detection. This is referred to as a Hybrid Automatic Repeat Request (HARQ).

Two known forms of HARQ are Chase combining and Incremental Redundancy (IR). Chase combining is a simplified form of HARQ wherein the receiver simply requests a retransmission of the same codeword again. IR is more complicated in that it provides for a retransmission of the code word using more parity bits. However, this involves a lowering of the code rate due to the added information, which can only be alleviated by further puncturing of bits. Conventional means of defining a puncturing pattern, such as a rate matching algorithm or alternatively a classical code puncturing matrix, as are known in the art, are unable to provide the necessary smooth and flexible transition between changing coding rates, as are envisioned for next generation communication products.

What is needed is an improved turbo coder that utilizes a unified puncturing scheme, which allows flexibility in choosing coding rates for the initial and subsequent transmissions. It would also be advantageous to provide this improvement using any of the combined ARQ techniques. It would also be of benefit to provide an improved turbo coder with a minimal increase of computational complexity or implementation effort.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages thereof, may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:

FIG. 1 shows a simplified block diagram for a turbo encoder as is known in the prior art;

FIG. 2 shows a simplified flow chart for a prior art coding structure;

FIG. 3 shows a simplified flow chart for a coding structure, in accordance with the present invention;

FIG. 4 shows a simplified block diagram for a turbo decoder, in accordance with the present invention;

FIG. 5 shows a chart for block interleaver management, in accordance with the present invention;

FIG. 6 shows simplified graphic representation for redundancy version, in accordance with the present invention;

FIG. 7 shows a chart for bit priority mapping, in accordance with the present invention;

FIG. 8 shows a matrix representation of a prior art puncture matrix;

FIG. 9 shows a set of puncturing matrices, in accordance with the present invention;

FIG. 10 shows a first graphical representation of the improvement provided by the present invention;

FIG. 11 shows a first graphical representation of the improvement provided by the present invention; and

FIG. 12 shows a simplified flow chart of a method, in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention provides a turbo coder that supports incremental redundancy (IR) as a form of ARQ combining, using a single, unified puncturing scheme. In particular, the present invention uses a puncturing scheme based on a block interleaver. Codeword bits are read in column-wise while the desired amount of unpunctured data is then read out row-wise after row and column rearrangement. The block nature of the interleaver ensures a regular puncturing distributed throughout the encoder trellis ensuring good code performance. The block puncturing approach of the present invention has the advantage of ease of implementation as well as retaining the flexibility in adapting to any desired coding rate without a significant increase in complexity. As a result, the present invention provides for flexible and fine-grained support of predefined redundancy versions at each transmission with progressive reduction in effective coding rates and support for full and partial forms of both Chase combining and IR. Preferably, the present invention also provides for symbol priority mapping onto the most reliable Quadrature Amplitude Modulation (QAM) constellation points to further reduce decoding errors.

In application, The High Speed Downlink Packet Access (HSDPA) feature of the Third Generation Partnership Project (3GPP) UTRA (UMTS Terrestrial Radio Access) or Wideband Code Division Multiple Access (WCDMA) system details a hybrid-ARQ scheme based on Incremental Redundancy (IR) methods applied to a rate-1/3 turbo-code. The present invention defines the High Speed Downlink Shared Channel (HS-DSCH) coding and modulation scheme to permit the use of incremental redundancy block interleaving in user equipment (UE), such as a cellular radio communication device. The present invention describes a specific method and apparatus for applying IR to HSDPA.

IR methods are known in the art, and have been applied before to systems such as Enhanced Data for GSM Evaluation (EDGE). However, the HSDPA problem is novel, in that the number of Soft Metric Locations (or SMLs) available to the Hybrid Acknowledge Repeat Request (HARQ) process can change depending on factors such as the number of ARQ processes in existence. The present invention allows for a change in the final coding rate according to the available coded symbol memory. Also, unlike the present invention, prior systems, such as EDGE, utilized convolutional codes rather than turbo-codes, and supported a different number of redundancy versions.

The present invention provides a flexible IR scheme specifically applicable to HSDPA. In particular, the IR scheme of the present invention supports: a) a flexible method of controlling the instantaneous and variable final code rate of the HARQ process (ranging from Chase combining to rate-1/3 expansion), b) general QAM modulation, including 16-QAM, c) a specific set of possible redundancy versions from which can be selected an optimal (or simply preferred) sequence of redundancy versions, based on the specific acknowledge/negative acknowledge (ACK/NACK) signal evolution applicable to HSDPA, and d) a novel implementation of block interleavers. Prior art implementations for IR, such as those of EDGE, do not meet the specific requirements of the current problem since they cannot change the final coding rate according to the available coded symbol memory. The terminal memory requirements of the user equipment are derived based on Chase (soft) combining at the maximum data rate defined by the associated UE capability parameters. In other words, the UE has memory limitations and can only accept particular code rates. The present invention accounts for these memory limitations and allows the UE to vary coding rates accordingly.

FIG. 2 shows the existing reference channel coding model for High Speed Downlink Packet Access (HSDPA) in accordance with the 3GPP specification protocols of section 4.2, “Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD) (Release 1999)”, TS 25.212 v3.5.0 (2000-12), which is hereby incorporated by reference. At a first stage 200 data is input as a concatenated transport stream of data blocks. To this stream, cyclic redundancy check (CRC) is added 202, and the code block are segmented 204 to produce N_(CB) code blocks 206. The detailed functionality of these blocks 200-206 is presented in TS 25.212. At this point, each of the code blocks are individually subjected to channel coding 208 and rate matching 210 for the puncturing and incremental redundancy used. The blocks are then subject to physical channel segmentation 212, interleaving 214, and physical channel mapping 216, where physical channels 1 through K are output. [maybe give overview of what goes on in each of these blocks? what does the box shading on the last two blocks signify?]

FIG. 3 shows a channel coding model for HSDPA in accordance with the present invention. The first four operations (transport block concatenation 200, CRC attachment 202, code block segmentation 204, and channel coding 208) proceed according to the 3GPP protocols previously described. Preferably, channel coding 208 proceeds according to a channel coder operable at a rate-1/3 turbo encoding function. In addition, the last three stages (physical channel segmentation 312, (second) interleaver 314, and physical channel mapping 316) also proceed similarly to the 3GPP protocols with the exception of operation on symbols instead of bits. The improvement of the present invention occurs in the first interleaver 300, redundancy version selection 302, and optional the bit priority mapper 304. [I see that rate matching 210 is not present. Where does rate selection occur in this diagram?]

FIG. 4 shows the operation of the first interleaver (300 in FIG. 3) in entering a codeword into puncturing matrices. In the puncturing scheme of the present invention, the unpunctured codeword bits are bit separated into respective “Systematic”, “Parity 1” and “Parity 2” streams denoted by X_(S,k), p_(1,k), p_(2,k) where kε{1, . . . , N_(info)}. Each stream is read into separate N_(row)×N_(col) block matrix interleavers. Preferably, the parity bits are combined into one puncturing matrix, but separate parity block interleavers can be used for each parity stream. In the preferred case of a single parity interleaver, x_(s),kε{1,0} and x_(P,k)={p_(1,k), p_(2,k)} where x_(P,k)ε{{1,0}, {0,1}, {1,0},{1,1}}. The tail bits from the coder are buffered separately and are later appended onto the unpunctured instantaneous codeword transmitted in a specific transmission time interval (TTI). The number of rows, N_(row), and number of columns, N_(col), in each interleaver can be variable and allocated dynamically. In a preferred embodiment, the number of rows, N_(row), is always fixed at thirty, while the number of columns, N_(col), is variable (dependent on the number of information bits N_(info)) and is determined in the same manner as the turbo code internal interleavers, such as is described in section 4.2.3.2.3.1 of “Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD) (Release 1999)”, TS 25.212 v3.5.0 (2000-12), which is hereby incorporated by reference.

FIG. 5 shows the data stream of the interleavers of FIG. 4. A novel aspect of the present invention is having data read in a column-wise fashion into each interleaver. The data includes dummy bits padded if N_(info)<N_(row)×N_(col), where y_(k)=x_(k) for k=1, 2, . . . , N_(info) and y_(S,k)ε{0,1} and y_(P,k) ε{{1,0}, {0,1}, {1,0}, {1,1}} for k={N _(info)+1, . . . , N_(row)×N_(col)}. These dummy bits are later removed when reading the codeword data row-wise from top-to-bottom from the block matrix, similar to the description in section 4.2.3.2.3.2 of TS 25.212, incorporated by reference.

To facilitate flexibility in supporting variable coding rates in the present invention, both columns and rows are permuted prior to reading out the block matrix contents. As an example of the benefit of row and column reordering, consider the case where N_(row)=30 and N_(col)=100. If the first two rows were to be read out without reordering, the codeword bits would correspond to the 29th, 30th, 59th, 60th, 89th, 90th, . . . stages in the encoder trellis. However, by reordering row 29 with row 15, then the transmitted codeword bits become those at the 15th, 30th, 45th, 60th, 75th, 90th, . . . stages in the encoder trellis, a more homogenous and therefore desirable distribution. In permuting the columns, it is ensured that no sub-block section of the trellis is neglected when only a portion of a row is read out to form the transmitted codeword. The row permutation is that defined by Table 7 in section 4.2.1.1 of TS 25.212, hereby incorporated by reference.

After the row and column permutation, the desired number of codeword bits can then be read out in row-wise fashion. Using the notation of FIG. 4, if the desired number of parity bits is an odd number and if x_(p,k)={p_(1,k), p_(2,k)} is the last symbol read from the parity interleaver, then the parity bit p_(1,k) is used as a codeword bit while the parity bit p_(2,k) is discarded. In the case of the parity interleaver, the maximum number of rows that can be transmitted N_(p,max) _(—) _(row) may be less than N_(row) due to UE memory restrictions, while for the systematic interleaver N_(s,max) _(—) _(row) is always equal to N_(row). If N_(SML) denotes the total number of Soft Metric Locations (SML's) provisioned at the UE, N_(tail) denotes the number of tail bits per code block, and N_(ARQ) _(—) _(proc) denotes the number of ARQ processes currently defined in the UE, then N_(p,max) _(—) _(row) is given by; $\begin{matrix} {N_{P,{max\_ row}} = {\min\left( {\left\lfloor \begin{matrix} {\quad{\frac{\quad N_{\quad{SML}}}{\quad{2 \times \quad N_{\quad{CB}} \times \quad N_{\quad{col}} \times \quad N_{\quad{ARQ\_ proc}}}}\quad -}\quad} \\ {\quad{\frac{\quad N_{\quad{row}}}{\quad{2 \times \quad N_{\quad{CB}}}}\quad - \quad\frac{\quad N_{\quad{tail}}}{\quad{2 \times \quad N_{\quad{col}} \times \quad N_{\quad{CB}}}}}} \end{matrix} \right\rfloor,N_{\quad{row}}} \right)}} & \left( {{Eq}.\quad 1} \right) \end{matrix}$

Note that all the independent variables in Eq. (1) are derivable at the UE following delivery of the signaled Hybrid Automatic Repeat Request (HARQ) information on the High Speed Downlink Secondary Control Channel (HS-DSCCH). When more coded bits are required than can be obtained by reading to the end of the N_(i,max) _(—) _(row) ^(th) row, iε{S,P}, reading may continue by wrapping around to the beginning of the first row, one consequence of which is to allow coding rates less than 1/3. Once the desired number of codeword bits is read from both block interleavers, the buffered tail bits are then appended completing the desired instantaneous codeword. The above equation defines the memory available to a UE (given that the systematic matrix is substantially fixed), and accounts for the available SML's per ARQ process. Using the above information a transmitting base station can choose the transmit rate suitable to work with the available memory by selecting particular block rows to output to fit the chosen rate, as will be described below. [at what step in FIG. 3 does rate selection occur? Claim 16] Moreover, the block interleaver is not used in conventional block interleaving per se, but is used to select rows from the block that are not punctured, so as to provide a higher equivalent code rate. [correct?]

Referring back to FIG. 3, the present invention also incorporates a redundancy version selector 302. Since a different number of codeword bits may be obtained from the systematic and parity block interleavers, the framework of the present invention allows for both Chase and incremental redundancy (IR) coding schemes. In order to support different redundancy versions, any row may be assigned as a starting point at which to commence the readout of codeword bits. Preferably, a static set of starting point combinations is pre-defined, as shown in FIG. 6. Although, smaller or larger sets of redundancy versions can be used, the eight redundancy versions (RVi,iε{0, . . . ,7}) shown require three bits for signaling in the HS-DSCCH with the following rules used to define all the versions shown.

Rule 1: Each rectangle represents rows 1 to N_(i,max) _(—) _(row) for iε{S,P}.

Rule 2: The X (e.g. RV1, RV2, RV3) signifies no bits are used from that interleaver to form the instantaneous codeword.

Rule 3: The double arrowed line signifies all bits in 1 to N_(i,max) _(—) _(row) in that block interleaver must be transmitted exactly once (e.g. RV0).

Rule 4: In the case there is an X in one interleaver and a single arrowed line in the other, then codeword bits are only read from the block interleaver with the single arrowed line.

Rule 5: In the case there is a double arrowed line in one interleaver and a single arrowed line in the other, then codeword bits are only read from the block interleaver with the single arrowed line once reading from the double arrowed line is complete.

Rule 6: In the case there is a single arrowed line in both interleavers, then codeword bits are read equally from both block interleavers.

Rule 7: If reading from a block interleaver with a single arrowed line has reached the end of line N_(i,max) _(—) _(row), but more codeword bits are required, then reading wraps around to line 1.

Rule 8: A fractional number N_(frac) _(—) _(num) beside the starting row of a single arrowed line indicates that starting row as N_(frac) _(—) _(num)×N_(i,max) _(—) _(row).

The present invention includes a specific set of eight redundancy versions for selecting coded bits from the systematic and parity interleavers in accordance with the above rules, as shown in FIG. 6 and as described below.

Redundancy version zero: the starting row is the top row of both the systematic and parity interleavers, and coded bits from the systematic interleaver is read from its starting row to completion before the remaining coded bits are read from the parity interleaver starting at its starting row.

Redundancy version one: the starting row is the top row of the parity interleaver, the coded bits are read from the parity interleaver starting at its starting row.

Redundancy version two: the starting row is N_(p,max) _(—) _(row)/3 for the parity interleaver, and the coded bits are read from the parity interleaver starting at its starting row.

Redundancy version three: the starting row is 2×N_(p,max) _(—) _(row)/3 for the parity interleaver, and the coded bits are read from the parity interleaver starting at its starting row.

Redundancy version four: the respective starting rows are the top row of the parity interleaver and N_(S,max) _(—) _(row)/2 for the systematic interleaver, and the coded bits are read equally from the systematic and parity interleaver starting at their respective starting rows.

Redundancy version five: the respective starting rows are N_(p,max) _(—) _(row)/4 for the parity interleaver and 3×N_(S,max) _(—) _(row)/4 for the systematic interleaver, and the coded bits are read equally from the systematic and parity interleaver starting at their respective starting rows.

Redundancy version six: the respective starting rows are the top row of the systematic interleaver and N_(p,max) _(—) _(row)/2 for the parity interleaver, and the coded bits are read equally from the systematic and parity interleaver starting at their respective starting rows.

Redundancy version seven: the respective starting rows are 3×N_(p,max) _(—) _(row)/4 for the parity interleaver and N_(S,max) _(—) _(row)/4 for the systematic interleaver, and the coded bits are read equally from the systematic and parity interleaver starting at their respective starting rows.

One aspect of these redundancy versions in the present invention is that their numbering does not suggest a particular order of transmission. For example, if on the first transmission RVO is signaled with enough codeword bits to result in a rate 3/5 code (exactly one third of the parity bits transmitted), the scheduler is permitted choose RV2 for the second transmission. Similarly, if in the first transmission, a rate 1/4 code is desired, RV4 might be selected for the second transmission. Moreover, systematic bits can be used in the first selected and unpunctured rows and parity bits in subsequent and punctured rows to reduce error. Using this approach, the chosen redundancy version can be used to support Chase, partial and full IR schemes in conjunction with any adaptive modulation and coding scheme (AMCS).

Referring back to FIG. 3, a preferred embodiment of the present invention incorporates a bit priority mapper (BPM), which further improves the performance of IR. Priority bit mapping is based on utilizing the differing bit reliability offered by higher order constellations (16-QAM or higher). It is well known that systematic portions of a turbo codeword are of greater importance to decoder performance than the parity portions. It naturally follows that system performance can be further improved by placing systematic bits in positions of high reliability if a higher order constellation is used.

The symbol mapping is dependent on the type of modulation and the number of systematic and parity bits used in transmission. As an example, if redundancy version 0 (RV0) is used with an effective code rate of 3/4 and 16-QAM modulation, each QAM symbol comprises of three systematic bits and one parity bit, while if the same version is used with a code rate of 1/2 and 16-QAM modulation, each QAM symbol then comprises of two systematic and 2 parity bits.

FIG. 7 shows an example of the proposed priority bit mapping for the case of 16-QAM modulation where a grouping of four bits is used to define one symbol. Here, the four bits are denoted i₁, q₁, i₂, q₂ with bits i₁ and q_(i) offering greater reliability than bits i₂ and q₂ due to the nature of the constellation, as is known in the art. Codeword bits are taken from the systematic and parity puncturing block interleavers and read into the BPM array in a column-wise manner. [corect?] The number of rows N_(row) _(—) _(BPM) of the BPM array is equal to log₂(M) where M is the constellation order, or N_(row) _(—) _(BPM)=log₂(16)=4 in the case of 16-QAM. The number of columns is N_(col) _(—) _(BPM)=480×K where K is the number of physical channels, as shown in FIGS. 2 and 3, and 480 is the number of modulated symbols on each channel.

Systematic codeword bits 700 are read from left-to-right into the BPM array one code block at a time. Once all systematic codeword bits 700 have been read in, parity codeword bits 702 are read in again from left-to-right and one code block at a time. The output of the BPM is a sequence of QAM symbols or bit vectors (a vector of four bits in the case of 16-QAM and a vector of two bits in the case of QPSK) given by the columns of the BPM array, read in sequence from left-to-right. Advantageously, this results in systematic bits 700 being mapped into the first rows of the bit mapper followed by subsequent mapping of parity bits. The puncturing matrix can then be chosen to select the rows of systematic bits to be unpunctured rows of the block for better accuracy. [correct? If not, why is having the systematic bits in the top row an advantage?] Optionally, it is also possible to reverse the sequence of high and low priority bits during a re-transmission of the same redundancy version to get further improved performance

Referring back to FIG. 3, the physical channel segmentation 312 proceeds according to the 3GPP protocol of section 4.2.10 of TS 25.212, incorporated by reference, but with a modification. Instead of applying the algorithm on bits as in section 4.2.10, it is applied on the QAM symbols/bit vectors output from the BPM described above.

Following channel segmentation 312, second interleaving 314, as described in section 4.2.1 1 in TS 25.212 is applied, again with a modification. In this case, instead of applying the interleaver on the bits comprising each physical channel, it is applied on the QAM symbols values or symbol indices of each of the physical channel which are output from the physical channel segmentation 312.

Finally and similarly, the physical channel mapping 314 described in section 4.2.12 of TS 25.212 is applied, again with substitution of QAM data symbols for bits.

EXAMPLE

The block-puncturing technique of the present invention was compared to that traditionally defined by puncturing matrices. Simulations were conducted for a rate-1/2 16-QAM coding and for a rate 3/4 QPSK coding for both Chase and full IR combining. FIG. 10 shows three curves representing spectral efficiency versus lor (power spectral density) at the base station over loc (total noise power) for the a rate-1/2, N=600, 16-QAM coding, over a Average White Gaussian Noise (AWGN) channel. The first curve 1000 represents the spectral efficiency of a signal using the traditional method of puncturing. The second curve 1002 represents the spectral efficiency of a signal using block puncturing in accordance with the present invention. The third curve 1004 represents the spectral efficiency of a signal using block puncturing and symbol mapping, in accordance with a preferred embodiment of the present invention. As can be seen there is no loss between traditional and block puncturing methods of the present invention, while the use of symbol mapping gives a significant advantage for 16QAM.

FIG. 11 shows the simulated error for a rate 3/4 QPSK coding for both Chase and full IR combining. In the case of Chase combining, the traditional puncturing pattern is defined by the matrix of FIG. 8 for all transmissions. [Is the systemic block interleaver punctured at all, or only the parity block interleaver? In what step of FIG. 3 does this puncturing take place? Claim 15] However, in the case of full incremental redundancy, in accordance with the present invention, the puncturing matrices for the respective first, second and third block transmissions are shown in FIG. 9, respectively. For the purposes of comparison, the same number of unpunctured bits was used for all transmissions, though the block-puncturing scheme of the present invention allows for variable transmission lengths. It should be noted that IR combining of one transmission is equivalent to the simplified Chase combining due to having only the one transmission.

The simulation was conducted to determine frame error rate (FER) for a Quadrature Phase Shift Keying (QPSK) signal at a 3/4 rate with a spreading factor (SF) of 16 and Orthogonal Variable Spreading Factor (OVSF) of 1 over an AWGN channel. The first curve 1100 shows the FER of the traditional IR scheme with one transmission (Chase combining). The second curve 1102 shows the FER of the traditional IR scheme with two transmissions. The third curve 1104 shows the FER of the traditional IR scheme with three transmissions. In comparison, and in accordance with the present invention, the fourth curve 1106 shows the FER of the block puncturing IR scheme with one transmission, the fifth curve 1108 shows the FER of the block puncturing IR scheme with two transmissions, and sixth curve 1110 shows the FER of the block puncturing IR scheme with three transmissions.

As can be seen, the block puncturing of the present invention so no loss of performance, for both Chase and IR schemes, in all cases except for in the three transmission, full incremental redundancy where there a slight loss in performance of the proposed block-puncturing scheme versus the more traditional yet very inflexible matrix based traditional puncturing approach. Considering the overall improvement provided by the present invention, this is quite acceptable. Moreover, symbol remapping may be used to alleviate deficiency.

FIG. 12 shows a flow chart representing a method of block puncturing for turbo code based incremental redundancy, in accordance with the present invention. A first step of the method is coding 1200, such as turbo coding, an input data stream into systematic bits and parity bits. A next step is loading 1202 loading the systematic bits and parity bits into respective systematic and parity block interleavers in a column-wise manner, as described previously. A next step is selecting 1204 a predetermined redundancy. This step follows the redundancy rules previously described, and preferably utilizes the specific redundancy version outlined above. A next step is outputting 1206 data from the block interleavers in a row-wise manner in accordance with the selected redundancy. Preferably, a outputting step includes mapping the bits from the systematic and parity block into a symbol mapping array wherein the systematic bits are mapped into the upper rows of the array and the parity bits are mapped into the lower rows of the array. This is followed by a step of selecting the final code rate dependant upon the available symbol memory, as defined by Eq. 1.

Although the invention has been described and illustrated in the above description and drawings, it is understood that this description is by way of example only and that numerous changes and modifications can me made by those skilled in the art without departing from the broad scope of the invention. Although the present invention finds particular use in portable cellular radiotelephones, the invention could be applied to any two-way wireless communication device, including pagers, electronic organizers, and computers. Applicants' invention should be limited only by the following claims. 

1. (canceled)
 2. (canceled)
 3. (canceled)
 4. (canceled)
 5. (canceled)
 6. (canceled)
 7. (canceled)
 8. (canceled)
 9. (canceled)
 10. (canceled)
 11. (canceled)
 12. (canceled)
 13. (canceled)
 14. (canceled)
 15. (canceled)
 16. (canceled)
 17. (canceled)
 18. (canceled)
 19. (canceled)
 20. (canceled)
 21. A method of bit priority mapping a turbo codeword, the method comprising the steps of: associating predefined disjoint areas of an array with differing bit reliability positions offered by a constellation; loading the punctured systematic turbo codeword bits and punctured parity turbo codeword bits into the array, giving higher priority to one set of bits when loading a predefined disjoint area; and continuously gathering bits from all distinct disjoint areas to form a symbol.
 22. The method of claim 21, wherein: the number of rows in the array is log₂(M) where M is the constellation order; sets of rows are associated with bit reliability positions offered by a constellation; data is read out of the array on a column wise basis each column wholly associated with one modulated symbol. 